The present invention relates to a charged particle beam equipment for examining and measuring semiconductor wafers, and in particular, to a waver exchange mechanism.
In an electron microscope for observing and examining an outer surface of a semiconductor wafer, it is required to rapidly exchange wafers to be examined having a size of up to 300 mm. Accordingly, it is required to shorten the waiting time until a next wafer to be examined is set in a sample chamber where a wafer is irradiated with a focused beam, after a preceding wafer is examined.
Referring to FIG. 9, explanation will be made of the background technology.
A wafer exchange-mechanism for wafers W (WA, WB) in a conventional electron microscope 80 comprises a sample chamber 81 in which a focused beam emitted from an electron optical system column 83 is irradiated to a wafer WA, and a plurality of load lock chambers 82a, 82b (two chambers in the case shown in the figure) which are adjacent to the sample chamber 81.
Further, while the wafer WA is irradiated with the focused beam in the center part of the sample chamber 81 so as to be examined, an unexamined wafer WB which will be exchanged at the next time is prepared in either one of the load lock chambers 82a, 82b. Specifically, as shown in FIG. 9, an unexamined wafer WB is introduced into the load lock chamber 82a from the outside, and the interior space therein is evacuated (Refer to the arrow D1).
Further, after the examination in the sample chamber 81 is completed, a sample stage 85 carrying thereon the examined wafer WA is set alongside the road lock chamber 82b (the arrow D2), as indicated in a solid line of FIG. 9, and then, a wafer exchange mechanism 84b is operated so as to withdraw the examined wafer WA (the arrow D3). Next, the sample stage 85 is set alongside the load lock chamber 82a (the arrow D4), and the wafer exchange mechanism 84a is operated so as to newly set the unexamined wafer WB on the sample stage 85 (the arrow D5). During this period, the examined wafer WA is delivered from the load lock chamber 82b (the arrow D6) while an unexamined wafer (which is not shown) is newly introduced into the lock chamber 82b. 
Further, the sample stage 85 is moved to a position directly below the photoelectric system column 83 at the center of the sample chamber 81 (the arrow D7) so as to start the examination of the wafer WB.
Thus, during the examination of the wafer WB, the load lock chamber 82b into which the unexamined wafer (which is not shown) to be next examined is introduced is evacuated.
Further, when the examination of the wafer WB is completed, the sample stage 85 carrying thereon the examined wafer WB is set alongside the load lock chamber 82b (the arrow D8) as indicated by the broken line in FIG. 9. Next, the wafer exchange mechanism 84a is operated to withdraw the examined wafer WB into the load lock chamber 82a (the arrow D9), and thereafter, it is delivered outside (the arrow D10). The above-mentioned steps will be repeated thereafter.
Thus, in the prior art configuration, with the provision of two load lock chambers 82a, 82b, the waiting time for exchanging the examined wafer WA and the unexamined wafer WB on the sample stage 85 has been aimed at being shortened. Further, the preparation of the next wafer to be examined is completed while the wafer is examined in the sample chamber 81, and the examination for the next wafer continuously follows as soon as the examination at present is completed. As stated above, it has been conventionally aimed at speeding up the examination of the wafer (Refer to for example, FIG. 1 in JP-A-10-261377).
Further, in a semiconductor examination apparatus which carry out an examination process for a semiconductor wafer under a depressurized atmosphere, it has been required to enhance through-put, to save footprint (to save foot space) and the like.
The reason as to the above-mentioned requirements is such that the mass production of semiconductor devices (enhancement of the production yield thereof) and reduction of an occupying space in a clean room according to the foot print saving can greatly contribute to cost reduction of the semiconductor devices.
In view of the above-mentioned background, in the semiconductor examination apparatus utilizing a charged particle beam, the vacuum sample chamber are provided with auxiliary exhaust chambers (load lock chambers) having a volume smaller than that of the vacuum sample chamber and isolated therefrom by gate valves through which they can be communicated with the vacuum sample chamber, and accordingly, semiconductor wafers or the like are introduced into or delivered from the vacuum sample chamber by way of the auxiliary exhaust chambers by means of a conveying device, or a transfer device.
With this configuration, the semiconductor wafers can be introduced into and delivered from the vacuum sample chamber without returning the pressure in the vacuum sample chamber to the atmospheric pressure (normal pressure), thereby it is possible to aim at enhancing the throughput by the examination device. That is, should the pressure in the vacuum sample chamber be returned to the atmospheric pressure each time when a semiconductor wafer is introduced into or delivered from the vacuum sample chamber, a much longer time would be required until the process is restarted after the vacuum sample chamber is depressurized, which results in low through-put.
Accordingly, there have been proposed or known various transfer devices which aim at enhancing the throughput in such a way that a semiconductor wafer or the like can be efficiently introduced into or delivered from the vacuum sample chamber in a short time without returning the pressure in the vacuum sample chamber to the atmospheric pressure each time when the semiconductor wafer or the like is introduced into or delivered from the vacuum sample chamber.
Conventionally, there has been generally known a multi-jointed arm type transfer device, which is configured such that a power is transmitted from a drive source located on the atmospheric side through the intermediary of a belt and pulleys so as to extend or shrink a whole of an arm portion composed of, for example, three linked arms, which are bendably connected in series. Further, as another type of the transfer device, there has been known a flog leg type transfer device having a rotary portion which is bendable like the so-called flog leg (Refer to, for example, JP-A-9-283588, paragraph 0023, and FIGS. 1 and 4, and JP-A-2001-118905, paragraphs 0019 to 0021, FIGS. 2, 3 and 6).
Further, conventionally, there has been known a transfer device which is composed of a pivot arm which is pivotably supported, a rotary arm which is bendably supported to a distal end of the pivot arm, and a sample carrying arm which is rotatably supported in its center part to the distal end of the rotary arm, and which therefore can transfer two semiconductor wafers at one time by its carrying parts provided at opposite ends of the sample carrying arm (For example, refer to JP-A-7-142551, paragraphs 0013 to 0017, and FIGS. 1 and 2).
Further, there has been conventionally known a flog leg type transfer device having two transfer arms and configured such that two multi-jointed arm type transfer arms which are bendably formed from first to third three arm parts are arranged point-symmetric with respect to a pivot center of the pivot shaft, and a wafer carrying part for carrying a semiconductor wafer on the distal end of the third arm part is provided to transfer two semiconductor wafers at one time (Refer to for example, JP-A-7-142552, paragraphs 0014 to 0020, FIGS. 1, 3 and 7).
Further, there has been known a transfer device configured such that short intermediate arms are rotatably supported respectively to opposite ends of a single rotary arm which is rotatably supported in its center part so as to be rotated by a drive source, so as to be rotated in association with the rotation of the rotary arm, and further, sample carrying arms (setting plates) for carrying thereon semiconductor wafers while rotating in association with the rotation of the intermediate arms are rotatably supported respectively to the distal ends of both of the intermediate arms so as to transfer two semiconductor wafers at one time (Refer to, for example, JP-A-8-195427, paragraphs 0011 to 0013 and FIGS. 1 and 2).